The present invention relates to a monolithic memory such as MOS dynamic memory.
FIG. 1 shows the schematic circuit arrangement of a prior-art dynamic memory employing N-type MOS transistors, which adopts the so-called address multiplex system of dividing address signals into the two groups of row addresses and column addresses and applying them through the same input terminal in a time-division fashion. The arrangement of FIG. 1 has the function, called "page mode", of successively changing only the column addresses with the row address fixed. In FIG. 1 and other drawings, reference symbols with suffixes R and C are assigned to circuit parts pertaining to a row selecting operation and a column selecting operation, respectively. Symbols 1R and 1C denote external control clocks. Principally, the former controls the start of the row selecting operation, and the latter the start of the column selecting operation. Circuits 2R and 2C receive the inputs 1R an 1C and generate a plurality of timing pulses necessary for operations within the memory, respectively. In the figure, among the timing pulses, only typical outputs 11R, 12R, 13R and 12C are mentioned with the others omitted. The circuit 2C responds to the signal 1C only under the condition that the signal 11R is applied thereto. An address input terminal 3 includes a plurality of signal lines for applying a plurality of bits of the row or column address in parallel. Address buffer circuits 4R and 4C receive the row address and column address applied through the terminal 3 in time division and deliver an internal row address signal 14R as well as its inverted signal 14R and an internal column address signal 14C as well as its inverted signal 14C in accordance with address buffer control signals 12R and 12C supplied from the circuits 2R and 2C, respectively. The signals 14R and 14R are supplied to a word line selector 5R which consists of a row decoder (not shown), drivers (not shown) for word lines W.sub.1 -W.sub.m, etc., while the signals 14C and 14C are supplied to a bit line selector 5C which consists of a column decoder (not shown), drivers (not shown) for bit line select lines Y.sub.1 -Y.sub.n, etc. Numeral 100 designates a memory cell array portion, which has pairs of bit lines B.sub.1 -B.sub.n as the so-called folded bit lines. A memory cell MC constructed of one MOS transistor is arranged at one of the two intersecting points between each bit line pair B.sub.1 -B.sub.n and each word line W.sub.1 -W.sub.m. Dummy cells (not shown) are also connected to the respective bit lines. A circuit 6R for sensing a minute signal from the memory cell MC is constructed of transistors Q.sub.1 and Q.sub.2, and is operated under the instruction of the sensor drive signal 13R supplied from the circuit 2R. A gate circuit 101 includes a pair of MOS transistors disposed every data line pair, and operates to connect an input/output data line pair I/O and the corresponding bit line pair in response to the signal of the line Y.sub.1 -Y.sub.m. Symbol 6C indicates a detector circuit, symbol 7C an output amplifier circuit, and numeral 8 an output terminal. Numeral 9 indicates a data input terminal, and symbol 10C a data input buffer. The various circuits in FIG. 1 are of the dynamic type. Hereunder, the operation of the circuit arrangement in FIG. 1 will be described with reference to FIG. 2.
When the row selection control clock 1R becomes its low level, the clock 12R among the plurality of internal clocks required for the internal operations is generated by the circuit 2R, while a row address .circle.R applied through the lines 3 in synchronism with the fall of the signal 1R is received by the circuit 4R. Thus, the internal address signals 14R and 14R are generated. Since this memory operates in accordance with the address multiplex system, only the row address .circle.R is first applied to the lines 3. .circle.C1 , .circle.C2 , .circle.C3 . . . .circle.Cj in FIG. 2 represent column addresses which are applied later.
In response to the internal address signals 14R and 14R, the circuit 5R operates to select one of the word lines W.sub.1 -W.sub.m, for example, W.sub.1. Thus, the plurality of memory cells connected to the selected word line W.sub.1 are read out. The respective bit lines are provided with the dummy cells (not shown), and the dummy cells which are connected to the bit lines pairing with the bit lines having the selected memory cells connected thereto are read out by the circuit 5R. In this way, minute signals are read out on the n pairs of bit lines. Thereafter, the signal 13R becomes its low potential, and the sensing circuits 6R are operated to differentially amplify the voltages of the corresponding data line pairs. With these operations, the row selecting operation is substantially completed.
Thereafter, when the column selection control clock 1C becomes its low level, the circuit 2C generates the signal 12C. The signal 11R is the inverted signal of the signal 1R, and the circuit 2C is so arranged as to respond to the fall of the signal 1C only when the signal 11R is at its high level. The circuit 2C responds to the rise of the signal 1C irrespective of the level of the signal 11R. In response to the signal 12C, the circuit 4C receives the column address .circle.C1 applied through the lines 3 in synchronism with the fall of the signal 1C and generates the internal address signals 14C and 14C. The circuit 5C responds to the signals 14C and 14C to select one of the bit line select lines Y.sub.1 -Y.sub.n, for example, Y.sub.1. Thus, the MOS transistors Q.sub.3 and Q.sub.4 of the gate circuit 101 turn "on", so that the signals of the data line pair B.sub.1 are transmitted to the input/output data line pair I/O and are differentially amplified by the detector 6C. The output of the detector 6C is further amplified by the output amplifier 7C, with the result that a read-out data .circle.1 is delivered to the output terminal 8.
In the ordinary mode, both the signals 1R and 1C are subsequently returned to their high potentials, and the memory is restored into the original stand-by status. The signals of the memory at this time assume levels indicated by dotted lines in FIG. 2.
More specifically, the circuit 2R has a circuit (not shown) which, when the signal 1R has become the high level, supplies the circuits relevant to the row selecting operation, e.g., 4R, 5R and 6R and the cell array portion 100 with signals for bringing them into stand-by states (i.e., precharged states). On the other hand, the circuit 2C has a circuit (not shown) which, when the signal 1C has become the high level, supplies the circuits relevant to the column selecting operation, e.g., 4C, 5C, 6C, 7C and 10C and the data line pair I/O with signals for precharging them into stand-by states.
On the other hand, in the page mode operation, after the output has appeared at the output terminal 8, the signal 1R is kept intact in the low potential state and only the signal 1C is turned "on" and "off" as indicated by solid lines in FIG. 2, whereby only the column selecting operations are successively carried out.
In the page mode, the signal 1R is in the low potential state. Therefore, the circuits relevant to the row selecting operation hold the previous states, in other words, the word line W.sub.1 is selected in the present example. In addition, the sensors 6R are held in the operative states. Accordingly, when the signal 1C falls into the high potential state, only the circuits relevant to the column selecting operation, e.g., the circuits 2C, 4C, 5C, 6C and 7C fall into the stand-by states since predetermined timings and make ready for the subsequent operation. Thereafter, when the signal 1C becomes the low potential, the circuits 2C and 4C operate as stated before, and the circuit 4C receives the next column address .circle.C2 applied through the lines 3 and supplies the signals 14C and 14C to the circuit 5C. The circuit 5C selects that one of the bit line pair select lines Y.sub.1 -Y.sub.n which corresponds to the signals 14C and 14C. The signals of the bit line pair corresponding to the bit line pair select line are transmitted to the input/output data line pair I/O, and a data is delivered to the output terminal 8 via the circuit 7C. Thenceforth, similar operations are continued, and data corresponding to the column addresses .circle.C3 , .circle.C4 . . . .circle.Cj are successively delivered to the terminal 8. Upon end of the page mode, both the signals 1C and 1R are returned to the high levels, and the memory is restored into the original stand-by status.
As described above, the row selecting operation is not repeated in the page mode. Therefore, the operation of higher speed than in the ordinary mode becomes possible. An access time during the page mode operation is equal to the period of time t.sub.CA from the reception of the column address to the delivery of the data, and this period of time t.sub.CA is about 1/2 to 2/3 of an access time t.sub.RA during the ordinary mode operation (the period of time from the reception of the row address to the delivery of the data).
The largest number of data j up to which the data can be successively read out in the page mode is equal, in principle, to the number n of the bit line pairs which can be appointed by column addresses, on the assumption that the data of the memory cells of different addresses are read out at all times. In memories of the address multiplex system, the number n of bit line pairs and the number m of word lines are usually equalized. The aforementioned largest number j therefore becomes .sqroot.N where N denotes the storage capacity of the whole memory. This value is the principle value, and can be properly altered in relation to the other characteristics. Usually, the largest number j of data lies in a range of from several tens to several hundred. In the page mode, different data in this amount can be successively read out in the aforementioned access times.
In using the memory as the main storage of an electronic computer, however, even the page mode described above is low in the access rate.